1. Field of the Invention
The present invention relates to memory integrated circuits. More particularly, the present invention relates to assembly buffers in memory integrated circuits.
2. The Prior Art
A memory integrated circuit includes a nonvolatile memory array unit such as a flash memory that is programmed in page mode. A volatile assembly buffer memory is connected to the memory array, and is at least a page in size so that an entire or partial page of data that is to be programmed may be stored therein.
Such an arrangement provides a single readily accessible and fully functional volatile memory that supports a variety of data operations such as providing data to the bit line driver (BLDRV) for nonvolatile memory programming, producing a target data compared with nonvolatile memory data when in program verify mode, and other operations including, in particular, operations that can benefit from the availability of a fast volatile memory to store an entire or partial page of program data, or to read data.
A bit line driver is connected to the assembly buffer memory and the memory array, and is at least a page in size so that an entire or partial page of data that is being programmed may be kept in the bit line driver during programming, thereby providing actual programming voltage or programming inhibit voltage to the memory array. As VCC levels decrease, and semiconductor processes employ much finer geometries including thinner oxide layers, narrower interconnect line spacing, and higher line resolution, the latched data can be damaged by more parasitic capacitance, and cross talk in the compact area. In addition, lower VCC levels and higher threshold voltage associated with the high voltage transistors is not enough to maintain the bit line driver data transferred from the assembly buffer memory.
FIG. 1 is a schematic diagram showing a typical prior-art assembly buffer memory and bit line driver that are used for programming a nonvolatile memory such as a flash memory in page mode. The assembly buffer memory is a type of latch circuit formed from low-voltage transistors to store programming data. The bit line driver is a high-voltage circuit.
In FIG. 1, n-channel MOS transistors 10, 12, 14, and 16, are low voltage transistors, which have relatively thin oxides and a low voltage operating range. Inverters 18, 20 and 22 are formed from low-voltage n-channel transistors. These components form the assembly buffer memory in which inverters 18 and 20 form a data latch. The data latch is loaded with data from the data-in driver when n-channel MOS transistor 16 is turned on by asserting the YS (Y-select) signal on its gate and n-channel MOS transistor 10 is turned on by asserting the LDABF (load assembly buffer) signal on its gate to force the latch to the state set by the input data. For example, a “zero” logic state at the data-in driver will force the input of inverter 18 to a low logic state and the feedback action of inverter 20 will reinforce that state after n-channel MOS transistor 10 has been turned off. YS is a y-select signal determined by a y-addresses signal and is used to select a specific assembly buffer memory through n-channel MOS transistor 16.
The data in the assembly buffer latch can be read by asserting the RDABF (read assembly buffer) signal on the gate of n-channel MOS transistor 14 and asserting the YS (Y-select) signal on the gate of n-channel MOS transistor 16. If a zero logic state has been stored in the latch as previously described, the output of inverter 18 will be at a high logic state, turning on n-channel MOS transistor 12. When n-channel MOS transistor 14 is turned on by asserting the RDABF (read assembly buffer) signal on its gate, the column line (COL) will be pulled low through n-channel MOS transistor 12. Persons of ordinary skill in the art will appreciate the actions that will result from the write and read operations if a “one” logic state is present at the data-in driver and is thus stored in the latch. Inverter 22 buffers the output of the latch presented to the bit line driver portion of the circuit.
The bit line driver includes p-channel MOS transistors 24 and 26, and n-channel MOS transistors 28, 30, 32, and 34. P-channel MOS transistors 24 and 26 are high voltage transistors, and n-channel MOS transistors 28, 30, 32, and 34 are also high-voltage transistors. Both n-channel and p-channel high-voltage transistors have relatively thicker oxides and a high-voltage operating range. P-channel MOS transistor 24 and n-channel MOS transistor 28 form a first high-voltage inverter and p-channel MOS transistor 26 and n-channel MOS transistor 30 form a second high-voltage inverter. Together these components form a high-voltage latch similar to the one formed by inverters 18 and 20 in the assembly buffer memory.
To program a nonvolatile memory cell, about −3 v is required on the bit line, and to prevent or inhibit a cell from being programmed, about +3 v is required on the bit line. Both high positive and negative voltages are supplied by the bit line driver, which is a type of latch circuit consisting of high-voltage transistors to supply the +3 v or −3 v to the bit line from one of the potentials VPY and VEY depending on the data in the assembly buffer memory. The latch may be loaded by turning on n-channel MOS transistor 36 by asserting the CLMPY signal on its gate while the VPY node is at VCC and the VEY node is at ground. After the data has been loaded, n-channel MOS transistor 36 is turned off and then the voltage at the VPY node is raised to, for example, +3V and the voltage at the VEY node is dropped to, for example, −3V. The data may then be written into the memory by turning on n-channel MOS transistor 32 by asserting the signal WRHV (write high voltage) at its gate at a level of, for example, +6V to pass the high voltage to the bit line BL. The contents of the memory cell connected to the bit line BL may be read by turning on n-channel MOS transistor 34 by asserting the COLSA (column sense amp) signal on its gate and turning on n-channel MOS transistor 16 by asserting the YS signal on its gate.
In the circuit of FIG. 1, signal nodes YS, LDABF, RDABF, LDAT, LDATB, LDATB1 and COL have an operating range of about VCC, which is assumed to be the lowest power supply voltage in the integrated circuit device. The signals LDABF (load assembly buffer) and RDABF (read assembly buffer) are common signals for all assembly buffer circuits. Node DL (data line) is connected to a sense amplifier or data-in driver.
Circuits like that shown in FIG. 1 suffer from certain weaknesses. First, LDABF is a common signal line for every assembly buffer memory. LDABF is high for all assembly buffer memory even if no data is to be written into assembly buffer memory, by having the signal YS low thus not turning on n-channel MOS transistor 16. For the unselected assembly buffer memory, charge sharing occurs between the input of inverter 18 and the column line COL through n-channel MOS transistor 10 when swinging the LDABF signal from ground to VCC.
Usually, to save layout area, inverters 18 and 20 are made very small in size and are therefore relatively weak. If the input to inverter 18 is at the VCC state latched by the feedback loop and the column line COL is in a floating state such as at ground potential, charge sharing can cause the input of inverter 18 to drop and the floating column line COL node to rise. If the voltage drop at the input of inverter 18 goes low enough to go beyond the logic threshold, the latched data will be flipped to the opposite polarity, resulting in the assembly buffer memory data to be destroyed unexpectedly. For the case in which the input of inverter 18 is low and the column line COL is floating at VCC, the same malfunction can occur in the other direction. Secondly, although the data line DL may experience the full swing between VCC and ground when driven by the data-in driver, the DL voltage, especially VCC, cannot be transferred to the column line COL node, because YS is VCC for a selected assembly buffer memory and there is a Vtn voltage drop across n-channel MOS transistor 16. That means that the column line COL can have only VCC−Vtn and not the full VCC. Under some design conditions, this dropped voltage on the column line COL is not enough to flip the assembly buffer memory latch data, meaning that careful design consideration must be given to the size of the transistor 10 and the transistors in inverters 18 and 20 to ensure writing operation.
There are other weaknesses in the circuit of FIG. 1. CLMPY has some protective voltage on n-channel MOS transistor 36 to protect and isolate the low-voltage transistor area from high voltages such as VPY and VEY which can reach +3 v and −3 v. For example, if the voltage at CLMPY is 1.8 v, the output of inverter 22 cannot be at a voltage higher than 1.8 v−Vt, where Vt is threshold voltage of n-channel MOS transistor 36. The data in the assembly buffer memory is transferred into BLDRV through n-channel MOS transistor 36, which is also a high-voltage transistor.
The detailed operation of the circuit of FIG. 1 can be understood by examining FIG. 2, which shows the various signal waveforms used to enter programming mode. The waveforms break into two groups in which one is for a program voltage (−3 v) to the bit line, and the other is for an inhibition voltage (+3 v) to the bit line. The first problem is observed when the signal WRHV at the gate of n-channel MOS transistor 32 is enabled by increasing it from 0 v to 6 v. As may be seen from FIG. 2, after the signal WRHV reaches a level of voltage high enough to turn on n-channel MOS transistor 32, the signals VEY and HLDAT (applying an inhibit voltage to the bit line), or VPY and HLDATB (applying a programming voltage to the bit line) have some glitches in a positive or negative direction depending on the initial condition of the bit line BL which is usually loaded by a relatively large capacitance. The positive or negative glitches can cause the high-voltage transistor latch to erroneously flip, because n-channel MOS transistor 36 is shut off to prevent leakage current through the transistor by the VEY bias right after the VEY supply starts pumping down. If the glitch is large enough to change the state of the latched data, an error might be associated with an addressed cell coupled to the bit line. The signal WRHV requires some special treatment to prevent that kind of problem.
Secondly, there is another major problem that exists due to the higher threshold voltage for the high-voltage transistors when VCC is low. From FIG. 2, it may be seen that VPY should stay at VCC before entering programming mode. During standby mode, BLDRV latch data is set through n-channel MOS transistor 36. Even though inverter 22 and n-channel MOS transistor 36 are strong enough to overcome the strength of p-channel MOS transistor 26 and n-channel MOS transistor 30, the high-voltage bit line driver latch is not in a normal operating mode, because p-channel MOS transistor 24, p-channel MOS transistor 26, n-channel MOS transistor 28, and n-channel MOS transistor 30 could be in an off state under some extreme conditions as previously mentioned. For instance, if the data out of inverter 22 is VCC, then HLDATB should be VCC, but if p-channel MOS transistor 24 and n-channel MOS transistor 28 are turned off because Vgs<Vth, the high-voltage bit line driver latch cannot guarantee the state of HLDAT. To supply negative voltage like VEY, the signal CLMPY must be shut off following application of the VEY voltage, then the high-voltage bit line driver latch is isolated from the assembly buffer memory. An unstable HLDAT can make the high-voltage bit line driver latch assume an opposite state. For the case of the output of inverter 22 being at ground, a similar problem occurs.
In the prior art as exemplified by the circuit of FIG. 1, a low-voltage assembly buffer circuit is separated from a high-voltage bitline driver circuit by a single isolation transistor 36. Because the lowest possible value of the supply voltage VCC can be lower than the highest possible threshold voltage for the bitline driver circuit, data may not be effectively transferred from the low-voltage assembly buffer circuit to the high-voltage bitline driver circuit.